(1) Field of the Invention
The present invention relates to a process used to fabricate dynamic random access memory, (DRAM), devices, and more specifically to a fabrication process, using novel process sequences to reduce the area of the DRAM cell.
(2) Description of the Prior Art
The semiconductor industry is continually striving to improve the performance of semiconductor devices, while still attempting to reduce the cost of these same semiconductor devices. The use micro-miniaturazation, or the use of sub-micron features, for fabrication of semiconductor devices, such as dynamic random access memory, (DRAM), devices, has allowed the performance and cost objectives to be partially realized. For example smaller features allow reductions in performance degrading capacitance, and performance degrading resistances to achieved, while the use of smaller devices, result in the attainment of a greater number of semiconductor chips, from a specific size starting substrate, however still possessing device densities equal to, or greater than, larger semiconductor chips, and thus resulting in a reduction of the processing cost for a specific semiconductor chip to be realized.
Micro-miniaturization has been mainly accomplished by advances in specific semiconductor fabrication disciplines, such as photolithography and dry etching. The use of more sophisticated exposure cameras, as well as the use of more sensitive photoresist materials, have allowed sub-micron images to be created in photoresist layers. In addition the development of more advanced dry etching tools and etch recipes, have allowed the sub-micron images in overlying photoresist layers to be successfully transferred to underlying materials, used in the creation of advanced semiconductor devices. However to achieve DRAM densities of 1 gigabit, or greater, new processing and structural enhancements may also be needed to supplement the advances gained through micro-miniaturization. Currently the area needed for a DRAM cell is equal to about eight times the square of the minimum feature used, sometimes referred to as 8F.sup.2. The creation of DRAM devices, with small areas are limited by basic features of the DRAM cell, such as the word line, bit line, as well as the space between word lines, needed for contact for overlying bit line, and stacked capacitor structures. Prior art, such as Tseng, in U.S. Pat. No. 5,710,074, describes the use of a conductive plug, contacting a portion of a source/drain region, with the conductive plug located between a word line and an isolation region, allowing an overlying stacked capacitor structure to contact underlying source/drain regions, via the conductive plug. However in that prior art the space used between the isolation region and the word line, needed for a storage node contact hole, and the conductive plug, is too large for 1 gigabit DRAM designs.
This invention will describe a novel fabrication process, enabling a DRAM cell with an area equal to 5F.sup.2, (2.5F by 2.0F), to be achieved. This is accomplished by reducing the space between word lines, needed for subsequent bit line contact to a source/drain region, to the minimum feature, (1F), used, while reducing the space between a word line and an isolation region, needed for stacked capacitor structure to source/drain contact, to 0.5F. The reduction in these spaces is made possible by forming self-aligned, epitaxial silicon plugs, between the word lines, and between a word line and an isolation region, where the word lines are encapsulated by a silicon nitride capping layer, and insulator spacers. The heavily doped N+, epitaxial silicon, is deposited at a low temperature, and selectively forms only on the exposed source/drain regions, located between word lines, and between a word line and an isolation region.